Faculty Profile
Personal Details
Name: Divya Kalpesh Shah
Gender: Female
Professional Details
Department: Electronics
Designation: Assistant Professor
Date of Joining: 2008-01-01
Area of Specialisation: VLSI DESIGN,HDL LANGUAGES(VHDL AND VERILOG),DIGITAL DESIGN, FPGA ,DTSP
Industrial Experience: 1
Teaching Experience: 11
Total Experience: 12
Educational Details
UG Qualification: B.E.
UG Year Of Passing: 2004
UG University: UNIVERSITY OF RAJASTHAN
UG Class: Distinction
PG Qualification: M.E.
PG Year Of Passing: 2011
PG University: MUMBAI UNIVERSITY
PG Class: Distinction
PHD Year Of Passing: 0
Research and Development
Number of Paper Published => National Conference: 3 International Conference: 5 International Journal: 2
Number of Workshops => Organised: 6 Attended: 15
Number of Talks Delivered => 3
National Conferences
| No. | Conf. Name | Conf. Location | Paper Title | Author Details | Proceeding No | Month & Year |
|---|---|---|---|---|---|---|
| 1) | National Conference on Fractional Calculus and Fractional Differential Equations | Savitribai Phule University, Pune | FPGA Implementation of Complex-order Derivative operator using CFE Tustin approximation method | Divya K. Shah, | - | Nov 2017 |
| 2) | NSCFET-17 | RAIT, Mumbai | Autonomous Robot Navigation using SLAM Algorithm | Sumit Jadhav,Aditya Dhanve,Divya K Shah, | - | Apr 2017 |
| 3) | NSCFET-17 | RAIT, Mumbai | FPGA Implementation of Image Enhancement using Histogram Equalization Technique | Deepika Lahane,Abhishek Nautiyal,Prithvi Shanbhag,Divya K. Shah | - | Apr 2017 |
International Conferences
| No. | Conf. Name | Conf. Location | Paper Title | Author Details | Proceeding No | Month & Year |
|---|---|---|---|---|---|---|
| 1) | International conference on Ubiquitous Computing | Pune | Simulation of Special Mathematical Functions | Sangeeth Sadanand,Divya K. Shah,Vishwesh V. Vyawahare, | - | Jul 2017 |
| 2) | IEEE international conference on Information Processing | Pune, Maharashtra | FPGA implementation of Efficient Vedic Multiplier | Khushboo Pichhode,M. D. Patil,Divya K. Shah,Rohit Chaurasiya | 0 | Dec 2015 |
| 3) | International Conference on communication, Information and Computing Technology, IEEE ICCICT-2015. | Mumbai | Vehicle Parking System Implementation using CPLD | Divya K Shah,Rohit Chaurasiya,Devdip Sen,Shashwat Goyal | 978-1-4799-5521-3 | Jan 2015 |
| 4) | CSCITA | Mumbai | FPGA Implementation of SVPWM Control Technique for Three Phase Induction Motor Drive Using Fixed Point Realization | Rohit Chaurasiya,Mukesh D. Patil,Divya Shah,Abhijit Kadam | 1569885215 | Apr 2014 |
| 5) | International Conference and workshop on emerging trends in technology(ICWET-2012) | Thakur college of Engineering and Technology | FPGA Implementation of Digital FIR Filter | Divya K. Shah,Poornima Talwai | 978-0-615-58717-2 | Jul 2012 |
International Journal
| No. | Conf. Name | Conf. Location | Paper Title | Author Details | Proceeding No | Month & Year |
|---|---|---|---|---|---|---|
| 1) | International Journal of Electronics and Communications (AEU), Elsevier | FPGA implementation of fractional-order chaotic systems | Divya K. Shah,Rohit B. Chaurasiya,Vishwesh A. Vyawahare,Khushboo Pichhode, Mukesh D. Patil | 1434-8411 | May 2017 | |
| 2) | IJCA | Simulink based Moving Object Detection and Blob Counting Algorithm for Traffic Surveillance | Mayur Salve,Dinesh Repale,Sanket Shingate,Divya Shah | 973-93-80875-07-5 | May 2013 |
Workshops Organised Details
| No. | Worked As | Name | Organised By | Location | No. of Days | Start Date | End Date |
|---|---|---|---|---|---|---|---|
| 1) | Coordinator | VHDL Programming and implementation using CPLD | RAIT | D. Y. Patil Campus, Nerul | 2 | 2017-09-16 | 2017-09-17 |
| 2) | Coordinator | VHDL Programming and implementation using CPLD | RAIT | D. Y. Patil Campus, Nerul | 2 | 2017-09-16 | 2017-09-17 |
| 3) | Coordinator | Cadence Simulation Software | RAIT | D. Y. Patil Campus, Nerul | 2 | 2017-08-05 | 2017-08-06 |
| 4) | Coordinator | Cadence Simulation Software | RAIT | D. Y. Patil Campus, Nerul | 2 | 2017-08-05 | 2017-08-06 |
| 5) | Coordinator | Hands-on-Training on Modern Digital design and Implementation using VHDL | RAIT | Nerul, Navi Mumbai | 2 | 2016-08-09 | 2016-08-08 |
| 6) | Coordinator | Hands-on-Training on Modern Digital design and Implementation using VHDL | RAIT | Nerul, Navi Mumbai | 2 | 2016-08-09 | 2016-08-08 |
| 7) | Coordinator | HANDS ON TRAINING: DIGITAL CIRCUIT IMPLEMENTATION USING CPLD AND FPGA | RAIT | D. Y. Patil Campus, Nerul | 2 | 2015-08-07 | 2015-08-08 |
| 8) | Coordinator | HANDS ON TRAINING: DIGITAL CIRCUIT IMPLEMENTATION USING CPLD AND FPGA | RAIT | D. Y. Patil Campus, Nerul | 2 | 2015-08-07 | 2015-08-08 |
| 9) | Coordinator | MODERN DIGITAL DESIGN USING KRYPTON | RAIT | D.Y. Patil Campus | 2 | 2014-08-08 | 2014-08-09 |
| 10) | Coordinator | MODERN DIGITAL DESIGN USING KRYPTON | RAIT | D.Y. Patil Campus | 2 | 2014-08-08 | 2014-08-09 |
| 11) | Committee Member | Application of Fractional Calculus in Engineering | RAIT | Nerul,Navi Mumbai | 3 | 2012-03-09 | 2012-03-11 |
| 12) | Committee Member | Application of Fractional Calculus in Engineering | RAIT | Nerul,Navi Mumbai | 3 | 2012-03-09 | 2012-03-11 |
Workshops Attended Details
| No. | Name | Organised By | Location | No. of Days | Start Date | End Date |
|---|---|---|---|---|---|---|
| 1) | VLSI and Embedded Systems | Terna Engineering College | Nerul, Navi Mumbai | 5 | 2008-08-06 | 2008-08-10 |
| 2) | Matlab and Simulink for Engineering Application | MathWorks India | Mathworks India Pvt Ltd | 1 | 2013-10-04 | 2013-10-04 |
| 3) | Modern Digital Design and Embedded System | E-Prayog,Virtual Lab,IIT Bombay | IIT Bombay, Powai | 2 | 2014-03-01 | 2014-03-02 |
| 4) | MATLAB and its Applications | RAIT | RAIT,Nerul | 3 | 2014-03-06 | 2014-03-08 |
| 5) | Two Day workshop on Embedded System Design using ARM mbed and Cypress PSoC | SPIT,Andheri | Andheri, Mumbai | 2 | 2015-05-11 | 2015-05-12 |
| 6) | AICTE approved Two Week FDP on Electronic System Design: From Devices to Applications | SPIT, Andheri | Andheri, Mumbai | 12 | 2015-05-04 | 2015-05-15 |
| 7) | Hardware Description Languages for Digital System Design | K.J. Somaiya College of Engineering | Vidyanagar, Vidyavihar, Mumbai | 5 | 2009-01-05 | 2009-01-09 |
| 8) | Signal Processing and Wavelets | RAIT | Nerul,Navi Mumbai | 3 | 2009-10-03 | 2009-10-05 |
| 9) | VLSI IC Design | SIT Lonavala and RFIC Solution Inc. | 105, Serra Way, Milpitas ,CA | 2 | 2009-10-28 | 2009-10-29 |
| 10) | Software Simulation | Saraswati College of Engineering with Automate Process control ISTE Chapter-MH172 | Kharghar,Navi Mumbai | 1 | 2010-09-16 | 2010-09-16 |
| 11) | Application of Fractional Calculus in Engineering | RAIT | Nerul,Navi Mumbai | 3 | 2012-03-09 | 2012-03-11 |
| 12) | INUP Hands-on Training Workshop on Nanofabrication Technologies | IIT Bombay | IIT Bombay, Powai,Mumbai | 4 | 2013-04-15 | 2013-04-18 |
| 13) | ARM University(UK) Program Certification course in Embedded System | Ramrao Adik Institute of Tecnology | Nerul, Navi Mumbai | 5 | 2015-07-10 | 2015-11-10 |
| 14) | Fractional Calculus Engineering Laboratory | VNIT, Nagpur | Nagpur | 5 | 2016-11-15 | 2016-11-19 |
| 15) | Cypress Programmable System on Chip (PSoC) | RAIT | D. Y. Patil Campus, Nerul | 1 | 2016-01-07 | 2016-01-07 |
Talks Delivered
| No. | Name | Organised By | Location | Date |
|---|---|---|---|---|
| 1) | VLSI and Embedded System Design | Dr. D. Y. Patil Polytechnic College | Nerul, Navi Mumbai | 2009-09-26 |
| 2) | Report Writing using LATEX | RAIT | Nerul, Navi Mumbai | 2012-09-14 |
| 3) | VHDL Programming | Department of Computer Engineering, RAIT | D.Y. Patil Campus | 2017-09-28 |