Faculty Profile
Personal Details
Name: Khushboo Pichhode
Gender: Female
Professional Details
Department: Electronics
Designation: Assistant Professor
Date of Joining: 2014-07-15
Area of Specialisation: FPGA, Microelectronics, VHDL, Digital Electronics
Industrial Experience: 1
Teaching Experience: 3
Total Experience: 4
Educational Details
UG Qualification: BE
UG Year Of Passing: 2011
UG University: Rajiv Gandhi Technical University, Bhopal
UG Class: Distinction
PG Qualification: ME
PG Year Of Passing: 2015
PG University: Mumbai University
PG Class: Distinction
PHD Year Of Passing: 0
Research and Development
Number of Paper Published => International Conference: 1 International Journal: 1
Number of Workshops => Organised: 4 Attended: 9
International Conferences
| No. | Conf. Name | Conf. Location | Paper Title | Author Details | Proceeding No | Month & Year |
|---|---|---|---|---|---|---|
| 1) | IEEE International Conference on Information Processing | Pune | FPGA Implementation of Efficient Vedic Multiplier | Khushboo Pichhode,Mukesh Patil ,Divya Shah,Rohit Chaurasiya | 978-1-4673-7758-4 | Dec 2015 |
International Journal
| No. | Conf. Name | Conf. Location | Paper Title | Author Details | Proceeding No | Month & Year |
|---|---|---|---|---|---|---|
| 1) | AEU-International Journal of Electronics and Communications | FPGA Implementation of Fractional-order Chaotic Systems | Divya k Shah,Rohit Chaurasiya,Vishwesh A Vyawahare,Khushboo Pichhode | 1434-8411 | May 2017 |
Workshops Organised Details
| No. | Worked As | Name | Organised By | Location | No. of Days | Start Date | End Date |
|---|---|---|---|---|---|---|---|
| 1) | Coordinator | VHDL Programming and Implementation using CPLD | Ramrao Adik Institute of Technology | Nerul | 2 | 2017-09-16 | 2017-09-17 |
| 2) | Coordinator | VHDL Programming and Implementation using CPLD | Ramrao Adik Institute of Technology | Nerul | 2 | 2017-09-16 | 2017-09-17 |
| 3) | Coordinator | Modern Digital Design and Implementation using VHDL | Ramrao Adik Institute of Technology | Nerul | 2 | 2016-09-02 | 2016-09-03 |
| 4) | Coordinator | Modern Digital Design and Implementation using VHDL | Ramrao Adik Institute of Technology | Nerul | 2 | 2016-09-02 | 2016-09-03 |
| 5) | Coordinator | Digital Circuit Implementation using FPGA and CPLD | RAIT | Nerul | 2 | 2015-08-07 | 2015-08-08 |
| 6) | Coordinator | Digital Circuit Implementation using FPGA and CPLD | RAIT | Nerul | 2 | 2015-08-07 | 2015-08-08 |
| 7) | Coordinator | Teaching Power Electronics with MATLAB/Simulink | RAIT | Nerul | 2 | 2015-07-31 | 2015-08-01 |
| 8) | Coordinator | Teaching Power Electronics with MATLAB/Simulink | RAIT | Nerul | 2 | 2015-07-31 | 2015-08-01 |
Workshops Attended Details
| No. | Name | Organised By | Location | No. of Days | Start Date | End Date |
|---|---|---|---|---|---|---|
| 1) | Participated in Robotics workshop conducted by ARK Technosolutions. | RAIT | Nerul | 3 | 2014-01-31 | 2014-02-01 |
| 2) | MATLAB and its Applications | RAIT | Nerul | 3 | 2014-09-26 | 2014-09-28 |
| 3) | Participated in “102nd INDIAN SCIENCE CONGRESS†| University of Mumbai | Kurla | 5 | 2015-01-03 | 2015-01-07 |
| 4) | Participated in a two-week ISTE Workshop on Control Systems conducted by IIT Kharagpur | Pillai's College | New Panvel | 10 | 2014-12-02 | 2014-12-12 |
| 5) | Participated in One day workshop on "FPGA Programming and Interfacing" | SPIT College | Andheri | 1 | 2015-06-30 | 2015-06-30 |
| 6) | Participated in workshop on "Research Trends in Control and Signal Processing (RTCSP-2015)" | RAIT | Nerul | 3 | 2015-07-17 | 2015-07-19 |
| 7) | Cadence Simulation Software | RAIT | Nerul, Navi Mumbai | 2 | 2017-08-05 | 2017-08-06 |
| 8) | Power Electronics Simulations using MATLAB/Simulink | Ramrao Adik Institute of Technology | Nerul | 2 | 2016-09-23 | 2016-09-24 |
| 9) | Cypress Programmable System on Chip (PSoC) | Ramrao Adik Institute of Technology | Nerul, Navi Mumbai | 1 | 2016-01-07 | 2016-01-07 |