Faculty Profile
Personal Details
Name: Amit Anand Bagade
Gender: Male
Professional Details
Department: Electronics & Telecommunication
Designation: Assistant Professor
Date of Joining: 2016-03-14
Area of Specialisation: Digital Circuits Design, VHDL, FPGA Design
Industrial Experience: 1
Teaching Experience: 5
Total Experience: 6
Educational Details
UG Qualification: B.E in Electronics Engineering
UG Year Of Passing: 2005
UG University: Mumbai University
UG Class: First Class
PG Qualification: M.Tech in Communication Systems
PG Year Of Passing: 2007
PG University: IIT Madras
PG Class: Distinction
PHD Year Of Passing: 0
Research and Development
Number of Workshops => Organised: 2 Attended: 6
Workshops Organised Details
| No. | Worked As | Name | Organised By | Location | No. of Days | Start Date | End Date |
|---|---|---|---|---|---|---|---|
| 1) | Coordinator | VHDL Workshop | RAIT | Nerul | 2 | 2018-08-30 | 2019-10-01 |
| 2) | Coordinator | VHDL Workshop | RAIT | RAIT, Dr. D. Y. Patil Vidyanagar, Sector-7, Phase 1, Nerul, Navi Mumbai-400706 | 2 | 2017-09-23 | 2017-09-24 |
| 3) | Coordinator | VHDL Workshop | RAIT | RAIT, Dr. D. Y. Patil Vidyanagar, Sector-7, Phase 1, Nerul, Navi Mumbai-400706 | 2 | 2017-09-23 | 2017-09-24 |
Workshops Attended Details
| No. | Name | Organised By | Location | No. of Days | Start Date | End Date |
|---|---|---|---|---|---|---|
| 1) | School of Pulsed Power Technology-2011 | VJTI | VJTI, Matunga, Mumbai-400019 | 5 | 2011-05-23 | 2011-05-27 |
| 2) | Two Week ISTE Workshop on Control Systems conducted by IIT Kharagpur | NMIMS MPSTME, Shirpur, Dhule | NMIMS MPSTME, Shirpur, Dhule | 11 | 2014-12-02 | 2014-12-12 |
| 3) | 3-Day Workshop on "Foundation of Fuzzy Set and Fuzzy Logic with Applications" | NMIMS MPSTME, Shirpur, Dhule | NMIMS MPSTME, Shirpur, Dhule | 3 | 2015-01-10 | 2015-01-12 |
| 4) | One Week Short Term Training Program on "Mathematical Modeling and Applications in Technology" | K. J. Somaiya Institute of Engineering and Information Technology | K. J. Somaiya Institute of Engineering and Information Technology, Sion, Mumbai-400022 | 5 | 2015-05-11 | 2015-05-15 |
| 5) | 3-Days Workshop on "FPGA Based Digital System Design using VHDL and System Generator in MATLAB (Hands on Practice) | Don Bosco Institute of Technology | Don Bosco Institute of Technology, Kurla(W), Mumbai-400070 | 3 | 2017-01-04 | 2017-01-06 |
| 6) | Hands-On-Training on "Introduction to MATLAB" | Ramrao Adik Institute of Technology | RAIT, Dr. D. Y. Patil Vidyanagar, Sector-7. Phase 1, Nerul, Navi Mumbai-400706 | 3 | 2017-01-09 | 2017-01-11 |