Name: Sangeeth Sadanand
Gender: Male
Department: Electronics
Designation: Assistant Professor
Date of Joining: 0000-00-00
Area of Specialisation: VLSI DESIGN,HDL LANGUAGES(VHDL AND VERILOG),DIGITAL DESIGN, FPGA
Industrial Experience: 0
Teaching Experience: 0
Total Experience: 0
UG Qualification: Electronics
UG Year Of Passing: 2014
UG University: University of Mumbai
UG Class: First Class
PG Qualification: Electronics
PG Year Of Passing: 2017
PG University: University of Mumbai
PG Class: First Class
PHD Year Of Passing: 0
Number of Paper Published => National Conference: 1 International Conference: 1
Number of Workshops => Organised: 2 Attended: 2